Reliability simulation is an area of increasing interest as it allows the design of circuits that are both reliable and optimized for circuit performance by transient device degradation calculations. In this paper, Hot Carrier (HC) injection mechanism and Negative Bias Temperature Instability (NBTI) effects on the performance of respectively n-channel and p-channel transistors of a 0.25μ CMOS technology are investigated using a new reliability simulation tool. Predicted degradation results are compared with HC and NBTI degradation models, developed on the bases of accelerated aging tests, in order to confirm simulator accuracy. The study concluded that after 10 years of operation, NMOS transistors present an increase of approximately 0.55V in linear threshold voltage and about 0.45V in saturation threshold voltage. Whereas, the linear and the saturation threshold voltages of PMOS transistors increase of only 38mV. Therefore, we can assert that HC degradation mechanism has more impact on NMOS than NBTI on PMOS transistors. Our study of reliability is extended to circuits' degradation to raise awareness of the circuit-level reliability simulator interest. Indeed, the degradation, caused by HC and NBTI, of a Ring Oscillator (RO), which designed with 40 serial OR delay gate looped on a NAND input, is presented in this paper. The effect of each mechanism on the frequency degradation is dissected. The study concluded that the increasing of the threshold voltage of both NMOS and PMOS transistors, under respectively HC and NBTI stress, increases the propagation delay of every RO stage. © 2016 IEEE.